Compact CMOS in wide bandgap semiconductor

ABSTRACT

CMOS Systems formed in Wide Bandgap Semiconductor and involving use of a material that forms a rectifying junction with either N and P-type Field Induced Semiconductor, in combination with, preferably, Parallel and Adjacent Channels subject to control by a Gate removed from said Channels by insulator.

This application is a CIP of Pending Applications Ser. No. 16/974,016Filed Sep. 8, 2020 and Ser. No. 17/300,746 Filed Oct. 18, 2021, andfurther Claims Benefit of Provisional Application Ser. No. 63/280,053Filed Nov. 16, 2021.

TECHNICAL FIELD

The present invention relates to Complementary Metal Oxide Semiconductor(CMOS) technology, and more particularly to, in a preferred embodiment,a Compact CMOS System formed in Wide Bandgap Semiconductor andcomprising a material which forms a rectifying junction with either Nand P-type Field Induced Semiconductor in combination with Parallel andAdjacent Channels subject to control by a Gate removed from saidChannels by insulator.

BACKGROUND

CMOS systems are well established, with an improvement in recent yearsbeing FINFET geometry, which had its origin about 20 or so years ago asdemonstrated by patent to Hu et al., U.S. Pat. No. 6,413,802 which isincorporated hereinto by reference. “FIN” is terminology given tosemiconductor projections from a planar surface of a semiconductorsubstrate as they resemble fins on fish. The geometry of the FIN allowsfor application of MOS. Gate Electrodes not only above a Channel of aMOSFET formed in a substrate, but also to Sides of the effective 3DStructure. There are literally thousands of FINFET references nowavailable, but none of which Inventor Welch is aware remotely disclosethe present invention.

Further, in recent years use of Wide Bandgap Semiconductors, such assilicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs),zinc oxide (ZnO); and diamond (C) are being applied in DeviceFabrication, mostly in the area Power Applications.

Continuing, Inventor Welch previously patented the use of material whichforms rectifying junctions with both N and P-type Silicon, whether theeffective doping type is metallurgical or field induced. See U.S. Pat.Nos. 6,624,493; 5,663,584; 5,760,449; 6,091,128 and 6,268,636, (all ofwhich are incorporated hereinto by reference). The listed patents toWelch report work performed under a Grant from the US Dept. of Energyunder Contract No. DE-FG47-93R701314, beginning in 1992. The work wasperformed in the 1990's and early 2000's at the University of NebraskaElectrical Engineering Dept. Another related patent to Welch is U.S.Pat. No. 4,696,093, upon which the DOE Grant was initially based. Inprior work, Inventor Welch had hands-on discovered that ChromiumDisilicide was formed in Silicon by annealing Chromium (deposited viaElectron beam or Sputtering onto Silicon) at about 600 degreesCentigrade, and said Chromium Disilicide forms rectifying junctions witheither both N and P-type Silicon. Welch discovered, when following up ona request from his Professor (R. S. C. Cobbold), that ChromiumDisilicide formed a very good rectifying with N-type Silicon during hisMasters work at Toronto in the early 70's when seeking to learn ifChromium deposited on SiO₂ migrated thereinto during a 600 degree C.anneal. (See “Migration of Ion-Implanted Krypton in Silicon DuringAnneal”, Welch, Davies and Cobbold, J. Appl. Physics, Vol. 48, No. 11,November 1977) for discussion of migration properties of AmorphizingKrypton ions implanted into silicon at various doses and energies duringanneal). That temperature was important as his DMOST-type fabricationprocess as that involved regrowth of an amorphized region at the surfaceof a substrate, into a single crystal thereby incorporating ionimplanted Boron and Phosphorous dopants onto electrically activesubstitutional sites in a single anneal, and while the anneal wasperformed Chromium was present as a self-aligned atop an SiO₂ GateDielectric. To investigate Chromium migration in SiO₂ during annealWelch applied Chromium to the back unpolished side of a substrate forelectrical contact purposes, upon which, on the polished side thereof,was formed a MOS Capacitor. Comparing Capacitance before and after the600 degree C. annealing resulted in the Capacitance decreasing when, ifanything, an increased Capacitance was expected due to Oxide thinningcaused by Chromium migration. The discovered effect was traced to theformation of a Capacitance providing rectifying junction on the roughunpolished backside of the substrate. (This was reported in his MASc.Thesis titled “Design and Fabrication of Sub-Micron Channel by DoubleIon Implantation”, MASC. Dissertation, University of Toronto, 1974. Seealso “Fabrication of Sub-micron Channel DMOST-Type MOSFTETS byIon-Implantation of Source, Drain and Channel”, ISAST Transactions onComputers and Intelligent Systems, No. 2, Vol. 3, 2011). InventorWelch's MASc. hands-on research resulted in operational Sub-micronChannel length DMOST-type MOSFETS fabricated by ion-implantationtechniques, rather than pre-deposition and drive-in diffusions.Literature searching in about 1984, soon after Inventor Welch hadcompleted his Law Degree at the University of Nebraska and tested intothe patent and Nebraska State Bar, turned up an article by Lepselter andSultanov titled “Some Properties of Chromium Doped Silicon”, in SovietPhysics Semiconductors“, Vol. 4, No. 11, Pages 1900-1902, May 1972described the formation of a rectifying junction when Chromium isdiffused into P-type Silicon. It was at that time Inventor Welchconceived using Chromium as a “dopant” in both N and P-type Silicon, toform a CMOS system and sought a Grant to investigate the effect. Thateffort eventually led to a Grant from the US Department of Energy (DOE).

A summary of the MASc. work, and the results of the work performed underthe DOE Grant are presented in an unpublished proposed Ph.D. Thesistitled “Mid-Bandgap Doped Junction, Single Semiconductor DeviceAlternative to Conventional Dual Device CMOS, Fabrication Thereof,Operational Results, and Analysis”. Said unpublished Thesis is availablefrom Inventor Welchat jdwscmosl@netzero.net In addition two articles“Mid-Bandgap Doped. Junction, Single Semiconductor Type DeviceAlternative to Conventional Dual Device CMOS”, Welch, ISAST Transactionson Electronics and Signal Processing, No. 1, Vol. 4, 2010, and “Insightto Operation of a Mid-Bandgap Doped Junction Single Semiconductor TypeDevice Alternative to Conventional Dual Device CMOS”, Welch, ISASTTransactions On Computers and Intelligent Systems, No. 1, Vol. 3, 2010),are also identified which report the same work.

Recently Inventor Welch studied FINFET systems, and in view thereof hasconceived a simple approach to fabricating a compact FINFET CMOS System,which is disclosed herein. There remains need for CMOS systems thatenable higher packing density of devices, and therefore prolong thevalidity of Moore's Law.

Also recently an old friend, Terry Pirruccello, alerted Inventor Welchto the use of Silicon Carbide in Semiconductors in Semiconductor DeviceFabrication.

Need remains for new Semiconductor Devices.

DISCLOSURE OF THE INVENTION

The Present invention is, in one embodiment, a CMOS structure comprisinga region of material in a wide bandgap substrate which forms rectifyingjunctions with both field induced N and P-type regions therein. SaidCMOS structure further comprises at least two channels projecting fromelectrical contact with said region of material in said wide bandgapsubstrate which forms rectifying junctions with both field induced N andP-type regions therein, and said CMOS structure further comprises gatestructures offset with respect to said channels by insulating material.The CMOS structure further comprises substantially non-rectifyingjunctions to said material which forms rectifying junctions with bothfield induced N and P-type wide bandgap semiconductor, and to distalends of said at least two channels.

Said wide bandgap semiconductor substrate, at least in the regions ofsaid channels can be characterized by a selection from the groupconsisting of:

-   -   it is substantially or per se. intrinsic;    -   it is substantially or per se. metallurigically compensated;    -   it contains both metallurgical N and P-type dopants in unequal        concentrations;    -   it is metallurgically doped to provide at least one area of        P-type material and at least one separate area of N-type        material in each channel region.

As is the case with all Present Invention CMOS Devices, in use a voltageis applied between the substantially non-rectifying junctions at thedistal ends of said at least two channels and a voltage is applied tosaid gate which, when switched between the voltages applied to thesubstantially non-rectifying distal ends of said at least two channels,causes a voltage to appear at the substantially non-rectifying junctionto said region of material which forms rectifying junctions with bothfield induced N and P-type wide bandgap semiconductor which is inverted,in that when the higher of said voltages applied to the substantiallynon-rectifying junctions to said distal ends of said at least twochannels is applied to said gate, the voltage at the substantiallynon-rectifying junction to said region of material which formsrectifying junctions with both field induced N and P-type siliconcarbide is low, and vice-versa.

For the purposes of this Specification, The terminology “Wide BandgapSemiconductor” refers to any Semiconductor material with a Bandgaplarger than silicon (Si), (which is about 1.1 eV) up to a Bandgap whichconstitutes an Insulator (eg. 6+eV). A Wide Bandgap Material can beselected from the group consisting of:

-   -   silicon carbide (SiC);    -   gallium nitride (GaN)    -   gallium arsenide (GaAs);    -   zinc oxide (ZnO); and    -   diamond (C).

A more specific Present Invention CMOS structure comprises a region ofmaterial in a silicon carbide substrate which forms rectifying junctionswith both field induced N and P-type silicon carbide. Said CMOSstructure further comprises at least two channels projecting fromelectrical contact with said region of material in a silicon carbidesubstrate which forms rectifying junctions with both field induced N andP-type silicon carbide, and said CMOS structure further comprises gatestructures offset with respect to said channels by insulating material.Said CMOS structure further comprises substantially non-rectifyingjunctions to said material which forms rectifying junctions with bothfield induced N and P-type silicon carbide, and to distal ends of saidat least two channels.

Said silicon carbide substrate, at least in the regions of said channelscan be characterized by a selection from the group consisting of:

-   -   it is substantially or per se. intrinsic;    -   it is substantially or per se. metallurigically compensated;    -   it contains both metallurgical N and P-type dopants in unequal        concentrations;    -   it is metallurgically doped to provide at least one area of        P-type material and at least one separate area of N-type        material in each channel region.

The material in said silicon carbide substrate which forms rectifyingjunctions with both field induced N and P-type silicon carbide, canvanadium doped silicon carbide.

The material comprising substantially non-rectifying junctions to saiddistal regions of channels can comprise nickel.

Another even more specific Present Invention compact CMOS structurecomprises a region of material in a silicon carbide substrate whichforms rectifying junctions with both field induced N and P-type siliconcarbide. Said compact CMOS structure further comprising at least twochannels projecting from electrical contact with said region of materialin a silicon carbide substrate which forms rectifying junctions withboth field induced N and P-type silicon carbide. Importantly in thisembodiment is that said channels are substantially parallel and adjacentto one another to provide a very compact result. Again, said compactCMOS structure further comprising a gate structure offset with respectto said channels by insulating material, and said compact CMOS structurefurther comprises substantially non-rectifying junctions to saidmaterial which forms rectifying junctions with both field induced N andP-type silicon carbide, and to distal ends of said at least twochannels.

Again, said silicon carbide substrate, at least in the regions of saidchannels can be characterized by a selection from the group consistingof:

-   -   it is substantially or per se. intrinsic;    -   it is substantially or per se. metallurigically compensated;    -   it contains both metallurgical N and P-type dopants in unequal        concentrations;    -   it is metallurgically doped to provide at least one area of        P-type material and at least one separate area.

As in the second embodiment said compact CMOS structure as can providethat the material in said silicon carbide substrate which formsrectifying junctions with both field induced N and P-type siliconcarbide, is vanadium doped silicon carbide. And the material comprisingsubstantially non-rectifying junctions to said distal regions ofchannels can comprise nickel.

In all embodiments the channels can be present in FINS which projectfrom a surface of said wide bandgap semiconductor substrate.

The Present Invention will be better understood by reference to theDetailed Description Section of the Specification, in conjunctions withthe Drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a perspective view of a prior art FINFET.

FIG. 2 shows a perspective view of a present invention Compact FINFETCMOS system.

FIG. 3 is shows a front elevational view of the FIG. 2 system, showingthe Insulator (I) between the Gate (G) and FIN (F2).

FIGS. 4 and 5 are adapted from patent to Welch, U.S. Pat. No. 6,624,493and serve to indicate the Inverting Nature of the present invention.

DETAILED DESCRIPTION

FIG. 1 shows a perspective view of a prior art early depiction of aFINFET, adapted from U.S. Pat. No. 6,413,802. This Figure is provided asit provides insight as to how inventor Welch herein conceived thepresent invention. Basically, replacing the Drain (D) with a Materialthat forms rectifying junctions with both N and P-type material, resultsin the present invention structure.

FIG. 2 shows a perspective view of a present invention Compact CMOSsystem in a planar substrate. Note the presence of a region of material(M) in a semiconductor substrate (SUB) which forms rectifying junctionswith both field induced N and P-type semiconductor. The compact CMOSstructure further comprises at least two Channels, (eg. indicated asFINS (F1) (F2)) projecting from electrical contact with said region ofmaterial in a semiconductor substrate which forms rectifying junctionswith both field induced N and P-type semiconductor (M), said FINS (F1)(F2) being substantially parallel and adjacent to one another to makethe system as compact as possible. Said compact CMOS structure furthercomprises a gate (G) structure offset with respect to said FINS (F1)(F2) by insulating material (I) as shown better in FIG. 3 . The compactCMOS structure further comprises substantially non-rectifying junctions(C1), (C2) and (MP) to said distal ends of said at least two FINSmaterial (F1) (F2) and to the Material (M), respectively. It is to beunderstood that a region out from under the Gate that providesindication of FINS (F1) and (F2) FIG. 2 is not meant to imply that anydistance must be present in a fabricated system, but is there only toallow indication (F1) and (F2). In a preferred embodiment there islittle such gap between the left and right side of the Gate (G) and thesubstantially non-rectifying junctions (C1) (C2) and (M).

It is noted that while FIG. 2 in particular shows Gate (G) Material overa relatively large area, it must be present only over Channel Regions(F1) and (F2). To reduce Gate Capacitance a significant area of Gate (G)Material can be removed leaving only Electrical Connected Material overChannel Regions. Is to be interpreted consistent with this.

FIG. 3 is included to as a front elevational view of the FIG. 2 system,showing the Insulator (I) between the Gate (G) and FIN (F2). Note thatthe Gate (G) can be a metal or a composite of metal and non-metalcomponents. Further, the Insulator under the Gate (G) can be muchthinner than at other locations, and/or the Gate (G) can be of a naturethat is present only above a Channel Region (F1) (F2), as FIG. 2 can beinterpreted to show, or it can be present on one of both sides and abovea FIN Channel region in a semiconductor substrate, as shown in FIG. 1 .The later point is not a determining factor as regards patentability.That, it is believed is found in the unique combination teachingsregarding application of material in a semiconductor substrate whichforms rectifying junctions with both field induced N and P-typesemiconductor in the identified patents by Welch, which teaching havenot previously been applied to systems comprising parallel adjacent FINSor channels (F1) (F2), and in the many FINFET related patents, such asU.S. Pat. No. 6,413,802 to Hu et al. Inventor Welch has combinedelements, each arguably present in various prior art publications, in anovel way he was positioned to appreciate resulting from a chancediscovery in his Masters work that Chromium annealed to N-type Siliconformed a very good rectifying junction, in combination with discovery ofthe previously mentioned Lepselter and Sultanov article which reportedChromium did likewise with P-type Silicon, all in combination withrecently developed insight to the FINFET structure which naturally lendsitself to providing substantially parallel and adjacent Channel regions(F1) (F2) which can both be conveniently subject to a single Gate (G)voltage in use. MOSFET structures that are formed from sequential N andP-Channel devices in N and P doped regions on a substrate must use asplit gate as did the results Welch reported in his previous patents.The present invention, again, does not require space consumingalternating N and P-type regions in a substrate, but rather uses only asubstantially Intrinsic or at least partially or substantiallycompletely Compensated substrate, in the region of substantiallyparallel and adjacent channels, to achieve a Compact CMOS system.

FIGS. 4 and 5 are adapted from patent to Welch, U.S. Pat. No. 6,624,493,amongst other publications by Welch, and serve to indicate the InvertingNature of the present invention. Said FIGS. show an exemplary biasingsituation wherein a Positive Voltage is applied to (C1), and (C2) isGrounded. The Ground could just as well be a Negative Voltage andtherefore FIGS. 4 and 5 are not limiting. Note that when the Gate (G)Voltage is at +V in FIG. 4 , the Midpoint (MP) of the present CompactFINFET CMOS system is at Ground (GND). FIG. 5 shows that when the Gate(G) Voltage is at Ground (GND), the Midpoint (MP) of the present CompactFINFET CMOS system is at +V, thus Inversion occurs. As perhaps betterdescribed in the previously mentioned unpublished Thesis by Welch, itshould be appreciated that the same Gate voltage is applied to Gates (G)in both Channel Regions (F1) and (F2). When the Gate Voltage is High at+V, electrons are attracted into both Cannels (F1) and (F2), which makesthe Lower junction D2 Forward Biased, and when Gate Voltage is Low atGround (or a negative value) Holes are pulled into both Channel Regions(F1) and (F2) the Upper junction (D1) is Forward-biased. In the FirstCase the voltage appearing at the Midpoint (MP) is Low and in the SecondCases the midpoint (MP) Voltage is high, thus Inversion is accomplished.It is also noted that an Off Side will present barriers to Conduction asa result of at least two sources. First a Channel Pinchoff Voltage(ΔV′), and Second a Channel Resistance (ΔV″) will be present.

It is noted that in Inventor Welch's earlier Single Device CMOSfabrication work under the previously mentioned DOE Grant, the twodevice channels (equivalent to the two FINS (F1) and (F2) weresequential, hence the Gate was split and the resulting S-CMOS deviceswere not very compact, much as is the case with conventional P-NJunction based CMOS systems. In the present Compact FINFET CMOS systemhowever, the substantially parallel and adjacent FINS (Channels) (F1)and (F2) are present adjacent to one another, and operated from a singleGate (G) structure. This is why the present FINFET system is compact.The present Device Configuration is not, to Inventor Welch's knowledge,remotely suggested in any prior art. It was only because of InventorWelch's prior experience that the Present Invention conceived. Note aswell that no N and P-type wells are necessary to fabricate P and NChannel MOSFETS as now Claimed. Inventor Welch did his earlier DOEsponsored fabrication of Single Device CMOS on Intrinsic Silicon, (seehis U.S. Pat. Nos. 6,624,493; 5,663,584; 5,760,449; 6,091,128 and6,286,636) and the previously mentioned Unpublished Thesis, but it isthought that use of Compensated Semiconductor might provide benefit,though there was not time to try that prior work. This lack of the needfor space consuming N and P-doped wells is another factor that enablesthe present system to be compact, and makes the present invention lessenergy intensive to realize. For emphasis, the major factor enabling thepresent invention is that some materials (M) form rectifying junctionswith either N or P-type filed induced effective doping n a Channelregion of a MOSFET. FIGS. 4 and 5 demonstrate the benefit that provides.A further consideration is that P-N junctions involve space-chargeregions which limit how small a channel can be without punch-throughoccurring. This is not a problem where the junctions are hot carriertype as in the present invention. It is believed patentability attachesto the Present Invention as it overcomes many problems associated withpreviously known CMOS structures, while importantly, providing a verycompact system via placement of channels adjacent to one another both ofwhich are influenced by a single Gate (G).

It is noted that “substantially non-rectifying” and “Substantiallyohmic” are to be read as equivalent herein.

The present invention in FIG. 2 can be viewed as a prior art FIG. 1system in which the Drain (D) is replaced with a region of material (M)that forms rectifying junctions with both field induced N and P-typesemiconductor, and the Gate (G) is expanded to cover more of the FIG. 1FIN Channels (F's). Nothing in Hu et al. 802 or any other knownreference remotely suggests that. Further nothing in Hu et al. 802remotely suggests that one skilled in the art of FINFET systems shouldseek out material that forms rectifying junctions with both fieldinduced N and P-type semiconductor. It is only because of InventorWelch's experience and insight in the area that he conceived the presentinvention. Further, Inventor Welch has found that his idea of usingmaterial that forms rectifying junctions with both field induced N andP-type semiconductor seems not to have been generally appreciated bypeople involved in solid state device design. A Professor at IllinoisUniversity for instance, when asked by the Government to evaluate hiswork based on his first patent in the area using Silicon as theSemiconductor—thoroughly trashed it. When Inventor Welch phoned thatProfessor and walked him through it, he commented that he had completelymissed the invention—and that Welch had performed Ph.D. level research.No further funding developed, however.

It is also noted that Terry J. Pirruccello is included as a Co-Inventorfor conceiving fabricating the Welch CMOS in Silicon Carbide.

Having hereby disclosed the subject matter of the present invention, itshould be obvious that many modifications, substitutions and variationsof the present invention are possible in view of the teachings. It istherefore to be understood that the invention may be practiced otherthan as specifically described, and should be limited only in itsbreadth and scope only by the Claims.

We claim:
 1. A CMOS structure comprising a region of material in a widebandgap substrate which forms rectifying junctions with both fieldinduced N and P-type regions therein, said CMOS structure furthercomprising at least two channels projecting from electrical contact withsaid region of material in a said wide bandgap substrate which formsrectifying junctions with both field induced N and P-type regionstherein; said CMOS structure further comprising gate structures offsetwith respect to said channels by insulating material; said CMOSstructure further comprising substantially non-rectifying junctions tosaid material which forms rectifying junctions with both field induced Nand P-type wide bandgap semiconductor, at distal ends of said at leasttwo channels; said wide bandgap semiconductor substrate, at least in theregions of said channels being characterized by a selection from thegroup consisting of: it is substantially or per se. intrinsic; it issubstantially or per se. metallurigically compensated; it contains bothmetallurgical N and P-type dopants in unequal concentrations; it ismetallurgically doped to provide at least one area of P-type materialand at least one separate area of N-type material in each channelregion; such that in use a voltage is applied between the substantiallynon-rectifying junctions at the distal ends of said at least twochannels and a voltage is applied to said gate which, when switchedbetween the voltages applied to the substantially non-rectifying distalends of said at least two channels, causes a voltage to appear at thesubstantially non-rectifying junction to said region of material whichforms rectifying junctions with both field induced N and P-type widebandgap semiconductor which is inverted, in that when the higher of saidvoltages applied to the substantially non-rectifying junctions to saiddistal ends of said at least two channels is applied to said gate, thevoltage at the substantially non-rectifying junction to said region ofmaterial which forms rectifying junctions with both field induced N andP-type silicon carbide is low, and vice-versa.
 2. A CMOS structure as inclaim 1, in which the wide bandgap semiconductor is selected from thegroup consisting of: silicon carbide (SiC); gallium nitride (GaN)gallium arsenide (GaAs); zinc oxide (ZnO); and diamond (C).
 3. A CMOSstructure comprising a region of material in a silicon carbide substratewhich forms rectifying junctions with both field induced N and P-typesilicon carbide, said CMOS structure further comprising at least twochannels projecting from electrical contact with said region of materialin a silicon carbide substrate which forms rectifying junctions withboth field induced N and P-type silicon carbide; said CMOS structurefurther comprising gate structures offset with respect to said channelsby insulating material; said CMOS structure further comprisingsubstantially non-rectifying junctions to said material which formsrectifying junctions with both field induced N and P-type siliconcarbide, and to distal ends of said at least two channels; said siliconcarbide substrate, at least in the regions of said channels beingcharacterized by a selection from the group consisting of: it issubstantially or per se. intrinsic; it is substantially or per se.metallurigically compensated; it contains both metallurgical N andP-type dopants in unequal concentrations; it is metallurgically doped toprovide at least one area of P-type material and at least one separatearea of N-type material in each channel region; such that in use avoltage is applied between the substantially non-rectifying junctions atthe distal ends of said at least two channels and a voltage is appliedto said gate which, when switched between the voltages applied to thesubstantially non-rectifying distal ends of said at least two channels,causes a voltage to appear at the substantially non-rectifying junctionto said region of material which forms rectifying junctions with bothfield induced N and P-type silicon carbide which is inverted, in thatwhen the higher of said voltages applied to the substantiallynon-rectifying junctions to said distal ends of said at least twochannels is applied to said gate, the voltage at the substantiallynon-rectifying junction to said region of material which formsrectifying junctions with both field induced N and P-type siliconcarbide is low, and vice-versa.
 4. A CMOS structure as in claim 3, inwhich the material in said silicon carbide substrate which formsrectifying junctions with both field induced N and P-type siliconcarbide, is vanadium doped silicon carbide.
 5. A CMOS structure as inclaim 3, in which the material comprising substantially non-rectifyingjunctions to said distal regions of channels comprises nickel.
 6. Acompact CMOS structure comprising a region of material in a siliconcarbide substrate which forms rectifying junctions with both fieldinduced N and P-type silicon carbide, said compact CMOS structurefurther comprising at least two channels projecting from electricalcontact with said region of material in a silicon carbode substratewhich forms rectifying junctions with both field induced N and P-typesilicon carbide, said channels being substantially parallel and adjacentto one another; said compact CMOS structure further comprising a gatestructure offset with respect to said channels by insulating material;said compact CMOS structure further comprising substantiallynon-rectifying junctions to said material which forms rectifyingjunctions with both field induced N and P-type silicon carbide, and todistal ends of said at least two channels; said silicon carbidesubstrate, at least in the regions of said channels being characterizedby a selection from the group consisting of: it is substantially or perse. intrinsic; it is substantially or per se. metallurigicallycompensated; it contains both metallurgical N and P-type dopants inunequal concentrations; it is metallurgically doped to provide at leastone area of P-type material and at least one separate area of N-typematerial in each channel region; such that in use a voltage is appliedbetween the substantially non-rectifying junctions at the distal ends ofsaid at least two channels and a voltage is applied to said gate which,when switched between the voltages applied to the substantiallynon-rectifying distal ends of said at least two channels, causes avoltage to appear at the substantially non-rectifying junction to saidregion of material which forms rectifying junctions with both fieldinduced N and P-type silicon carbide which is inverted, in that when thehigher of said voltages applied to the substantially non-rectifyingjunctions to said distal ends of said at least two channels is appliedto said gate, the voltage at the substantially non-rectifying junctionto said region of material which forms rectifying junctions with bothfield induced N and P-type silicon carbide is low, and vice-versa.
 7. Acompact CMOS structure as in claim 6, in which the material in saidsilicon carbide substrate which forms rectifying junctions with bothfield induced N and P-type silicon carbide, is vanadium doped siliconcarbide.
 8. A compact CMOS structure as in claim 6, in which thematerial comprising substantially non-rectifying junctions to saiddistal regions of channels comprises nickel.
 9. A CMOS structure as inclaim 1, in which said channels are present in FINS which project from asurface of said wide bandgap semiconductor substrate.
 10. A CMOSstructure as in claim 3, in which said channels are present in FINSwhich project from a surface of said wide bandgap semiconductorsubstrate.
 11. A compact CMOS structure as in claim 6, in which saidchannels are present in FINS which project from a surface of said widebandgap semiconductor substrate.